1. Field of the Invention
The present invention relates to fractional-N phase-lock loops (PLLs), and in particular, to fractional-N PLLs with a delay line loop (DLL).
2. Description of the Related Art
Referring to FIG. 1, a fractional-N PLL is used to digitally synthesize signal frequencies using a non-integer counter 22 (integer plus fraction) in its feedback path. The fractional portion F of the counter 22 provides finer tuning resolution for a given reference frequency (originating from a reference oscillator 12) than an integer only counter. For a given tuning resolution, the fractional-N counter 22 has a smaller modulus than an integer counter and, therefore, results in faster phase lock and produces less close-in phase noise in the voltage-controlled oscillator (VCO) 20.
However, such fractional counters 22 have been notorious for generating undesirable spurious noise at the fractional frequencies. Spurious noise elements ("spurs") occurring at the fractional frequency rate are introduced, typically, as a result of either poorly calibrated fractional delays within the loop or voltage dithering in the loop filter 18 due to the PLL charge being distributed over time.
One of the more common methods for performing a fractional count is that of integer averaging. For example, in order to obtain a fractional modulus of N+1/4 the counter 22 will divide by the modulus N for three successive cycles and then divide by N+1 for one cycle. At any given point in time, the instantaneous division is incorrect, but averaged over four cycles such division provides exactly N+1/4. However, the three successive cycles of division by N cause the loop phase error to accumulate in one direction, while the fourth cycle of division by N+1 causes one large phase error in the opposite direction. While the desired average frequency is thus maintained, these "jumps" in phase nonetheless produce signals at spurious frequencies which are related to the reference frequency.
In another approach involving fractional-N counters, a variable amount of electrical charge is injected into the loop filter 18 during each cycle of the reference signal 15 in an attempt to null out charge imbalances and eliminate voltage dither within the loop filter 18. However, this technique still tends to dump into the filter 18 electrical charge which is spread over time and still results in some amount of voltage dithering.
Referring to FIG. 2, another common fractional-N implementation adds a variable delay element 24 after the fractional-N counter 22 for supplementing the integer VCO delay steps. Since the counter 22 begins counting over each cycle without waiting for the output 25 of the delay element 24, each successive delay within the delay element 24 must be adjusted to cancel out the accumulated phase error. Delivery of a consistent N+1/4 output period would require division by N for three consecutive cycles accompanied by additional delay of 1/4, 2/4 and 3/4 of a VCO output period, respectively, followed by a division by N+1 with no added delay ("0/4"). If each one of such delays is a properly calibrated fractional percentage of the integer VCO period, each successive cycle will then be aligned in phase with the signal 15 from the reference counter 14, thereby resulting in minimal tuning line dither being produced by the phase detector 16. However, maintaining such proper calibration of each of the supplemental delays is difficult to do consistently.
Referring to FIG. 3, this technique can be represented as shown based upon a VCO signal period of one microsecond and corresponding delays of 1/4 of a VCO output period or 0.25 nanoseconds. The accumulator 26, which is a 4-bit adder, sums its summation output 27a with the fractional information 31b and is clocked by the output 23 from the fractional-N counter 22. The carry output 27b of the accumulator 26 serves as the modulus control signal M for the counter 22, and instructs the counter 22 to add the one additional count when more than one full VCO period of phase lag has accumulated (thereby preventing the variable delay gate range from being exceeded). The summation signal 27a is also used to increment the delays within the delay element 24.
Referring to FIG. 4, one conventional technique for maintaining calibration of the fractional replicas of the VCO period is to use a frequency-divided output 41a of the VCO 20 (FIG. 1) as a time reference within a DLL. This signal 41a is frequency-divided by two D-type flip-flops 46, 48 which are clocked by the prescaler output 41b of the counter 22. The first flip-flop output 47 drives a ramp generator 50, while the second output 49 clocks the accumulator 26 and drives the DLL phase detector 44. The output 51 of the ramp generator 50 is compared against two threshold signals 41c, 41d in two threshold comparators 42, 52, with the first result signal 43 also driving the DLL phase detector 44 and the second result signal 23 driving the PLL phase detector 16.
The first threshold signal 41c is generated by a digital-to-analog converter (DAC) DAC1 (not shown). The second threshold signal 41d is generated by a circuit which sums the output of another DAC DAC2 with the output 27a from the accumulator 26.
The slope of the ramp signal 51 is modulated by a control signal 45 generated by the DLL phase detector 44 (by adjusting the value of the output from a constant current source which charges a capacitor within the ramp generator 50). When the input 47 to the ramp generator 50 is asserted, the ramp signal 51 rises at a constant rate beyond the threshold voltage 41c, thereby generating a pulse at the output 43 which is compared in phase to the frequency-divided VCO signal 49. This modulation feedback of the delay introduced by the ramp generator 50 forces the delay from node A to node C to equal the period of the prescaler output signal 41b.
The second threshold comparator 52 compares the ramp signal 51 to a threshold voltage 41d which is equal to or greater than the first threshold voltage 41c, depending upon the value of the summation output 27a from the accumulator 26. Hence, the corresponding delay in the phase of this comparator output 23 is modulated by the state of the output 27a from the accumulator 26.
Referring to FIG. 5, if a known calibration period t.sub.43a is established with the signal path set by threshold comparator 42, then an incremental change in the time delay (.DELTA..sub.1 =t.sub.23a -t.sub.43a) can be obtained which is proportional to the threshold voltages 41c (V.sub.41c), 41d (V.sub.41d) which are applied along the signal path as established by threshold comparator 52 (t.sub.23a =t.sub.43a *V.sub.41d /V.sub.41c).
While this circuit 40 provides for some calibration of the fractional VCO delay steps, a number of sources for errors still exist. For example, errors in matching the delay paths, e.g., the threshold comparators 42, 52, or errors in the symmetry of the charge pump within the DLL phase detector 44 will introduce fractional calibration errors.
Accordingly, it would be desirable to have a DLL which provides more accurate and consistent self-calibration of its fractional delays.